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1. Features
* Low-voltage and Standard-voltage Operation
- 1.8 (VCC = 1.8V to 5.5V)
* Internal Organization
- 64 x 16 Three-wire Serial Interface 2 MHz Clock Rate (5V) Compatibility Self-timed Write Cycle (5 ms max) High Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years * 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages * Lead-free/Halogen-free Devices
* * * *
Three-wire Serial EEPROM
1K (64 x 16)
2. Description
The AT93C46E provides 1024 bits of serial electrically-erasable programmable readonly memory (EEPROM) organized as 64 words of 16 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT93C46E is available in space-saving 8lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages. The AT93C46E is enabled through the Chip Select pin (CS) and accessed via a threewire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output DO pin. The write cycle is completely self-timed and no separate erase cycle is required before write. The write cycle is only enabled when the part is in the erase/write enable state. When CS is brought high following the initiation of a write cycle, the DO pin outputs the ready/busy status of the part. The AT93C46E is available in 1.8V (1.8V to 5.5V) version.
AT93C46E
8-lead PDIP
Table 2-1.
Pin Name CS SK DI DO GND VCC NC
Pin Configuration
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply No Connect
CS SK DI DO
1 2 3 4
8 7 6 5
VCC NC NC GND
8-lead SOIC
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC NC GND
8-lead TSSOP
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC NC GND
Rev. 5207D-SEEPR-1/08
Absolute Maximum Ratings*
Operating Temperature......................................-55C to +125C Storage Temperature .........................................-65C to +150C Voltage on Any Pin with Respect to Ground ........................................ -1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 2-1.
Block Diagram
MEMORY ARRAY 64 X 16
ADDRESS DECODER
DATA REGISTER OUTPUT BUFFER MODE DECODE LOGIC
CLOCK GENERATOR
Table 2-2. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol COUT CIN Note: Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI) This parameter is characterized and is not 100% tested. Max 5 5 Units pF pF Conditions VOUT = 0V VIN = 0V
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Table 2-3. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, (unless otherwise noted)
Symbol VCC1 VCC2 VCC3 ICC ISB1 ISB2 ISB3 IIL IOL VIL1 VIH1(1) VIL2(1) VIH2(1) VOL1 VOH1 VOL2 VOH2 Note:
(1)
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage
Test Condition
Min 1.8 2.7 4.5
Typ
Max 5.5 5.5 5.5
Units V V V mA mA A A A A A V V V V
VCC = 5.0V VCC = 1.8V VCC = 2.7V VCC = 5.0V VIN = 0V to VCC VIN = 0V to VCC 2.7V VCC 5.5V 1.8V VCC 2.7V 2.7V VCC 5.5V 1.8V VCC 2.7V
Read at 1.0 MHz Write at 1.0 MHz CS = 0V CS = 0V CS = 0V
0.5 0.5 0.4 6.0 10.0 0.1 0.1 -0.6 2.0 -0.6 VCC x 0.7
2.0 2.0 1.0 10.0 15.0 1.0 1.0 0.8 VCC + 1 VCC x 0.3 VCC + 1 0.4
IOL = 2.1 mA IOH = -0.4 mA IOL = 0.15 mA IOH = -100 A VCC - 0.2 2.4
0.2
V V
1. VIL min and VIH max are reference only and are not tested.
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Table 2-4. AC Characteristics Applicable over recommended operating range from TA = -40C to + 85C, VCC = +2.7V to + 5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol fSK Parameter SK Clock Frequency Test Condition 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V Relative to SK 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V Min 0 0 0 250 250 1000 250 250 1000 250 250 1000 50 50 200 100 100 400 0 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 0.1 1M 3 100 100 400 250 250 1000 250 250 1000 250 250 1000 100 150 400 5 Typ Max 2 1 0.25 Units MHz
tSKH
SK High Time
ns
tSKL
SK Low Time
ns
tCS
Minimum CS Low Time
ns
tCSS
CS Setup Time
ns
tDIS tCSH tDIH
DI Setup Time CS Hold Time DI Hold Time
Relative to SK Relative to SK Relative to SK
ns ns ns
tPD1
Output Delay to "1"
AC Test
ns
tPD0
Output Delay to "0"
AC Test
ns
tSV
CS to Status Valid
AC Test
ns
tDF tWP Endurance
(1)
CS to DO in High Impedance Write Cycle Time 5.0V, 25C
AC Test CS = VIL
ns ms Write Cycle
Note:
1. This parameter is ensured by characterization.
3. Functional Description
The AT93C46E is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic "1") followed by the appropriate op code and the desired memory address location.
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Table 3-1.
Instruction READ EWEN ERASE WRITE ERAL WRAL EWDS
Instruction Set for the AT93C46E
Address SB 1 1 1 1 1 1 1 Op Code 10 00 11 01 00 00 00 x 16 A5 - A0 11XXXX A5 - A0 A5 - A0 10XXXX 01XXXX 00XXXX Comments Reads data stored in memory, at specified address Write enable must precede all programming modes Erase memory location An - A0 Writes memory location An - A0 Erases all memory locations. Valid only at VCC = 4.5V to 5.5V Writes all memory locations. Valid only at VCC = 4.5V to 5.5V Disables all programming instructions
READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic "0") precedes the 16bit data output string. ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical "1" state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS ). A logic "1" at pin DO indicates that the selected memory location has been erased and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be written into the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic "0" at DO indicates that programming is still in progress. A logic "1" indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A ready/busy status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle, tWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic "1" state and is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V 10%.
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ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.
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AT93C46E
4. Timing Diagrams
Figure 4-1. Synchronous Data Timing
s (1)
Note:
1. This is the minimum SK period.
Table 4-1.
Organization Key for Timing Diagrams
AT93C46E I/O AN DN x 16 A5 D15
Figure 4-2.
READ Timing
tCS
High Impedance
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Figure 4-3.
CS
EWEN Timing(1)
tCS
SK
DI
1
0
0
1
1
...
Note:
1. Requires a minimum of nine clock cycles.
Figure 4-4.
CS
EWDS Timing(1)
tCS
SK
DI
1
0
0
0
0
...
Note:
1. Requires a minimum of nine clock cycles.
Figure 4-5.
CS
WRITE Timing
tCS
SK
DI
1
0
1
AN
...
A0
DN
...
D0
DO
HIGH IMPEDANCE
BUSY
READY
tWP
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AT93C46E
Figure 4-6.
CS
WRAL Timing((1)),( (2))
tCS
SK
DI
1
0
0
0
1
...
DN
...
D0
DO
HIGH IMPEDANCE
BUSY READY
tWP
Notes:
1. Valid only at VCC = 4.5V to 5.5V. 2. Requires a minimum of nine clock cycles.
Figure 4-7.
ERASE Timing
tCS
CS
CHECK STATUS
STANDBY
SK
DI
1
1
1
AN
AN-1
AN-2
...
A0 tSV tDF
HIGH IMPEDANCE READY
DO
HIGH IMPEDANCE
BUSY
tWP
Figure 4-8.
ERAL Timing(1)
tCS
CS
CHECK STATUS
STANDBY
SK
DI
1
0
0
1
0 tSV tDF
HIGH IMPEDANCE READY
DO
HIGH IMPEDANCE
BUSY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
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AT93C46E Ordering Information
Ordering Code AT93C46E-PU (Bulk Form only) AT93C46EN-SH-B(1) (NiPdAu Lead Finish) AT93C46EN-SH-T(2) (NiPdAu Lead Finish) AT93C46E-TH-B(1) (NiPdAu Lead Finish) AT93C46E-TH-T Notes:
(2)
Package 8P3 8S1 8S1 8A2 8A2
Operation Range
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
(NiPdAu Lead Finish)
1. "B" denotes bulk. 2. "-T" denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.
Package Type 8P3 8S1 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Small Outline Package (TSSOP) Options -1.8 Low Voltage (1.8V to 5.5V)
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AT93C46E
Part marking scheme:
AT93C46E 8-PDIP
TOP MARK Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark
| | | |---|---|---|---|---|---|---|---| A T M L U Y W W |---|---|---|---|---|---|---|---| 4 6 E 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot)
AT93C46E 8-SOIC
TOP MARK Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark
| | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 4 6 E 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot)
AT93C46E 8-TSSOP
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TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 4 6 E 1 |---|---|---|---|---| BOTTOM MARK |---|---|---|---|---|---|---| C00 |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 Indicator Y = SEAL YEAR 6: 7: 8: 9: 2006 2007 2008 2009 0: 1: 2: 3: 2010 2011 2012 2013 WW = SEAL WEEK 02 04 :: :: = = : : Week Week :::: :::: 2 4 : ::
50 = Week 50 52 = Week 52
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AT93C46E
5. Packaging Information 8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
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Revision History
Doc. Rev. 5207D 5207C 5207B 5207A Date 1/2008 11/2007 8/2007 1/2007 Comments Removed `preliminary' status Modified `max' value on AC Characteristics table Modified Part Marking Scheme Tables Initial document release
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support s_eeprom@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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5207D-SEEPR-1/08

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